1. Field of the Invention
The present invention relates to forming nitride read only memory (NROM), and more particularly, to a method of forming an NROM embedded with mixed-signal circuits.
2. Description of the Prior Art
Nitride read only memory (NROM) is a semiconductor device for data storage. It is composed of a plurality of memory cells. Each of the memory cells comprises a MOS transistor and an ONO gate dielectric layer. Since the silicon nitride layer in the ONO gate dielectric layer is a highly dense material, hot electrons can be trapped in the silicon nitride layer by way of tunneling through the MOS transistor, in order to store data. Although NROM has an advantage of a two bit multi-storage function, a simpler manufacturing process than similar products, such as flash ROM, and being widely welcomed by the market, it is not good enough to just make conventional improvements. Because, the semiconductor industry is orienting itself toward the development of system on chip (SOC) products, in other words, products in which are simultaneously manufactured memory devices and the circuits devices, so as to make a single chip comprise memory and mixed-signal circuits. In U.S. Pat. No. #5,908,311, a method of forming a mixed-signal circuits comprising the flash ROM is proposed. Based on different characteristics and applications of NROM and flash ROM, it is a very important issue to develop a system on chip which integrates NROM and mixed-signal circuits.
Please refer to FIG. 1 to FIG. 10. FIG. 1 to FIG. 10 are schematic diagrams of a process for making the mixed-signal circuits comprising flash ROM. As shown in FIG. 1, the mixed-signal circuits comprising flash ROM according to the prior art are made on a surface of a semiconductor substrate 10. The semiconductor substrate 10 comprises a P+substrate 12, and a Pxe2x88x92epi layer 14. The surface of the semiconductor substrate 10 comprises a memory area 11 and a periphery area 13. The periphery area 13 further comprises a 3-volt transistor area 15 and a 5-volt transistor area 17. An N-well region 16 of MOS, a P-well region (not shown) of MOS, a channel stop implant 18, and at least a field oxide region (FOX) 22 are in the periphery area 13. A P-well region 23 is in the memory area.
The prior art method is to form a sacrificial oxide layer 24 on the surface of the semiconductor substrate 10 first, then perform a first photolithography process and form a first mask 25 in order to expose the 5-volt transistor region 17 in the N-well region 16. Thereafter, perform a first ion implantation process in order to adjust the threshold voltage of the 5-volt transistor (not shown) in the N-well region 16. After that, perform a second photolithography process and a second ion implantation process in order to adjust the threshold voltage of the 5-volt transistor (not shown) in the P-well region (not shown).
As shown in FIG. 2, after adjusting the threshold voltage of the 5-volt transistor (not shown), the sacrificial oxide layer 24 is removed completely. Then form a sacrificial oxide layer 28 on the surface of the semiconductor substrate 10. Thereafter, perform a third photolithography process to expose the memory region 11 by utilizing a third mask 32. Then perform a third ion implantation process in order to adjust the threshold voltage of the memory cell (not shown).
As shown in FIG. 3, after adjusting the threshold voltage of the memory cell (not shown), remove the sacrificial oxide layer 28 in the memory area 11, then remove the third mask 32. After that form a sacrificial oxide layer 34 in the memory area 11. The formation of the sacrificial oxide layer 34 will contribute to a thickness increase of the sacrificial oxide layer 28 in the periphery region 13. However, the growth rate of the sacrificial oxide layer 34 is obviously larger than that of the sacrificial oxide layer 28 in this process step.
As shown in FIG. 4, form a first polysilicon layer 36 on the surface of the sacrificial oxide layer 28, the sacrificial oxide layer 34 and the field oxide layer 22, then perform a fourth photolithography process and form a fourth mask 37. The fourth mask 37 exposes the predetermined site 39 of the resistor in the periphery area 13 and the memory area 11. Thereafter, perform a fourth ion implantation process in order to dope the predetermined site 39 of the resistor in the periphery area 13 and the memory area 11 with low doping. After that remove the fourth mask 37. Then perform a fifth photolithography process (not shown) and a fifth ion implantation process (not shown) in order to dope the region outside of the predetermined site 39 of the resistor in the periphery area 13 and the memory area 11 with high doping.
As shown in FIG. 5, perform a sixth photolithography process in order to form a sixth mask 41. The sixth mask 41 exposes the 3-volt transistor region 15 and defines the resistor 38, the bottom electrode 42 of the capacitor, the gate 44 of the 5-volt transistor (not shown) and the floating gate 46 of the flash ROM cell (not shown). Then, perform a first etching process in order to remove the first polysilicon layer 36 not covered by the sixth mask 41 and form at least a resistor 38, a bottom electrode 42 of the capacitor, a gate 44 of the 5-volt transistor (not shown) and the floating gate 46 of the flash ROM cell (not shown) on the semiconductor substrate 10. Thereafter, remove the sixth mask 41.
As shown in FIG. 6, form a bottom oxide-nitridetop oxide(ONO) 48 structure on the semiconductor substrate 10 that covers the resistor 38, the bottom electrode 42 of the capacitor, the gate 44 of the 5-volt transistor(not shown), the floating gate 46 of the flash ROM cell(not shown), the exposed field oxide layer 22 and the gate oxide layer 28 in the 3-volt transistor region 15. Then, perform a seventh photolithography process in order to form a seventh mask 49. The seventh mask 49 exposes the 3-volt transistor region 15. Thereafter, perform a second etching process in order to remove portions of the ONO layer 48 not covered by the seventh mask 49. After that, remove the seventh mask 49.
Please refer to FIG. 7. Perform an eighth photolithography process in order to form an eighth mask 52 on the surface of the ONO layer 48. The eighth mask 52 exposes the 3-volt transistor region 15 in the N-well region 16. Thereafter, perform a sixth ion implantation process in order to adjust the threshold voltage of the 3-volt transistor (not shown) in the N-well region 16. After that, perform a third etching process in order to remove the gate oxide layer 28 in the 3-volt transistor region 15, then remove the eighth mask 52. Thereafter, form a gate oxide layer 54 atop the 3-volt transistor region 15. After that, perform a ninth photolithography process and a seventh ion implantation process in order to adjust the threshold voltage of the 3-volt transistor (not shown) in the P-well region. Since the manufacturing of the 5-volt transistor (not shown), the resistor 38, the capacitor 54 and the flash ROM cell (not shown) occurs earlier than the manufacturing of the 3-volt transistor (not shown), the effect on the 3-volt transistor (not shown) resulting from improper heat treatment is avoided.
As shown in FIG. 8, form a second polysiliocn layer 56 on the semiconductor substrate 10 that covers the gate oxide layer 54, the exposed field oxide layer 22 and the ONO layer 48. Then, perform a doping process to the second polysiliocn layer 56. Thereafter, as shown in FIG. 9, perform a tenth photolithography process in order to form a ninth mask 57 on the surface of the second polysilicon layer 56. The ninth mask 57 defines the gate 58 of the 3-volt transistor (not shown), the top electrode 62 of the capacitor 64 and the control gate (not shown) of the flash ROM cell (not shown). After that, perform a fourth etching process to completely remove portions of the second polysilicon layer 56 not covered by the ninth mask 57 and form at least a gate 58, a top electrode 62 of the capacitor 64 and a control gate 55 of the flash ROM cell (not shown) on the semiconductor substrate 10.
As shown in FIG. 10, perform an eleventh photolithography process in order to form a tenth mask 63, the tenth mask 63 covering the 3-volt transistor region 15, the resistor 38 and the capacitor 64, and define the gate 44 of the 5-volt transistor 66. Then, perform a fifth etching process in order to remove the ONO layer 48 and the first polysilicon layer 36 not covered by the tenth mask 63. Finally, remove the ninth mask 57 and the tenth mask 63 and complete the manufacturing of the 3-volt transistor 68 and the flash ROM cell 72.
After completing the above process, form an oxide layer for sealing the polysilicon layer on the semiconductor substrate 10. Then, perform a pocket ion implantation process optionally to the drain of the flash ROM cell 72 by forming a mask and performing angled implantation. Finally, perform a back-end process. The back-end process is the same as a general adapted back-end process and comprises forming the lightly doped drain (LDD) of the transistor in the periphery area, the contact hole, the via and the metal layer. The mask for forming the lightly doped drain also exposes the source of the flash ROM cell 72.
According to the prior art method for forming the flash ROM comprising mixed-signal circuits, not only are the process steps very complex and lead to a high cost, but there is also only one choice for the composition of the dielectric layer of the capacitor. Also, in regard to the functionality of devices, the flash ROM can only store one bit each time. In other words, it does not have a multi-storage function. Therefore, it is a very important subject to improve or resolve the above mentioned issues.
It is therefore a primary objective of the present invention to provide a method of forming a nitride read only memory (NROM) embedded with mixed-signal circuits on a semiconductor substrate so as to achieve an objective of forming a system on chip (SOC).
It is therefore another objective of the present invention to preserve different dielectric layers of a capacitor by adjusting a cleaning and an etching process. For example, the combination of the dielectric layer of the capacitor can be top oxide-nitride-bottom oxide (ONO), nitride-bottom- oxide (NO), or bottom oxide(O) to provide the capacitor with varied dielectric constants in order to match the mixed-signal circuits.
It is therefore another objective to make the control gate of the NROM, the top electrode of the capacitor, the resistor and the gate of the MOS in the periphery area from the same polysilicon layer in order to reduce process steps and complexity of manufacturing. Briefly, the method according to the claimed invention comprises: (1) providing a semiconductor substrate, the surface of the semiconductor substrate comprising a memory area and a periphery area; (2) forming a bottom electrode of a capacitor atop an isolation layer in the periphery area; (3) forming an ONO layer that covers the memory area, the periphery are and the bottom electrode of the capacitor, the ONO layer comprising a bottom oxide layer, a silicon nitride layer and a top oxide layer; (4) forming a plurality of longitudinal bit line masks on the surface of the ONO layer in the memory area; (5) performing a first ion implantation process of a first conductive type at an angle not perpendicular to the ONO layer in order to form a plurality of pocket doping areas of the first conductive type in a region of the substrate not covered by the bit line mask; (6) etching a predetermined thickness of the bit line mask; (7) performing a second ion implantation process of a second conductive type in order to form a plurality of bit lines of the second conductive type in regions of the substrate not covered by the bit line mask; (8) removing the bit line mask; (9) removing the ONO layer on the active area in the periphery area and forming a plurality of ion wells in the active area; (10) performing a wet etching process in order to etch and clean the surface of the active area in the periphery area and etch a predetermined thickness of the dielectric layer of the capacitor; (11) performing at least one oxidation process in order to simultaneously form a gate oxide layer with a specific thickness in the active area in the periphery area and a thermal oxide layer atop each of the buried bit lines in the memory area; (12) forming a polysilicon layer, then performing a first photolithography process and a first anisotropic etching process in order to define a gate, a top electrode of the capacitor and a resistor in the periphery area and a control gate in the memory area; and (13) performing a third ion implantation process of a first or a second conductive type in order to adjust a resistivity value of the resistor.
It is an advantage of the present invention that the method of forming the NROM embedded with mixed-signal circuits can preserve different combinations of dielectric layers of the capacitor by adjusting the cleaning and etching processes, and further provide the capacitors with various dielectric constants in order to match with mixed-signal circuits. Moreover, the present invention only needs one polysilicon layer to fabricate the control gate of the NROM, the top electrode of the capacitor, the resistor and the gate of the MOS in the periphery area. Therefore, the process steps are simplifed and the cost is reduced.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.